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vhdl语言设计一个8路彩灯控制器？

library ieee;

use ieee.std_logic_1164.all;

entity fengxi is port(

q:in std_logic_vector(5 downto 0);

rst,adjust,clk:in std_logic;

y:out std_logic_vector(7 downto 0));

end;

architecture behavioal of fengxi is

type states is (s0,s1,s2,s3,s4,s5,s6);

signal state:states;

signal k:integer range 0 to 3;

signal en,clk_low,clk_use:std_logic;

signal y_out,y_out1:std_logic_vector(7 downto 0);

begin

process(clk,rst)-分频

begin

if rst='1' then

k=0;clk_low='0';

else

if(clk'event and clk='1') then

if k=3 then

k=0; clk_low=not clk_low;

else

k=k+1;

end if;

end if;

end if;

end process;

process(clk,adjust)==调速

begin

if adjust='1' then

clk_use=clk;end if;

if adjust='0' then

clk_use=clk_low;

end if;

end process;

process(q)-手动

begin

if q="000000" then en='1';else en='0'; end if;

if q="000001" then y_out1="00000001";end if;

if q="000010" then y_out1="00000010";end if;

if q="000100" then y_out1="00000011";end if;

if q="001000" then y_out1="00000100";end if;

if q="010000" then y_out1="00000101";end if;

if q="100000" then y_out1="00000110";end if;

end process;

process(rst)-循环

begin

if (rst='1') then

state=s0;else

if(clk_use'event and clk_use='1') then

case state is

when s0 =

state=s1;

when s1=

state=s2;

when s2=

state=s3;

when s3 =

state=s4;

when s4=

state=s5;

when s5=

state=s6;

when s6=

state=s1;

end case;

end if;

end if;

end process;

process(rst,q)

begin

if rst='1' then

y_out="00000000";

else

case state is

when s0=

y_out="00000000";

when s1=

y_out="00000001";

when s2=

y_out="00000010";

when s3=

y_out="00000011";

when s4=

y_out="00000100";

when s5=

y_out="00000101";

when s6=

y_out="00000110";

end case;

end if;

if en='1' then

y=y_out;end if;

if en='0' then

y=y_out1;end if;

end process;

end;

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